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  1/13 december 2001 n high speed: f max = 170 mhz (typ.) at v cc =5v n low power dissipation: i cc =1 m a (max.) at t a =25 c n high noise immunity: v nih =v nil = 28% v cc (min.) n power down protection on inputs n symmetrical output impedance: |i oh |=i ol = 8 ma (min) n balanced propagation delays: t plh @ t phl n operating voltage range: v cc (opr) = 2v to 5.5v n function compatible with 74 series 74 n improved latch-up immunity description the 74v2g74 is an advanced high-speed cmos single d-type flip flop with preset and clear fabricated with sub-micron silicon gate and double-layer metal wiring c 2 mos tecnology. a signal on the d input is transfered to the q and q outputs during the positive going transition of the clock pulse. clear and preset are independent of the clock and accomplished by a low setting on the appropriate input. power down protection is provided on all inputs and 0 to 7v can be accepted on inputs with no regard to the supply voltage. this device can be used to interface 5v to 3v. all inputs and outputs are equipped with protection circuits against static discharge, giving them esd immunity and transient excess voltage. 74v2g74 single d-type flip flop with preset and clear pin connection and iec logic symbols order codes package t & r sot23-8l 74v2g70str sot323-8l 74v2g70ctr sot23-8l sot323-8l
74v2g74 2/13 input equivalent circuit pin description truth table x= don't care logic diagram this logic diagram has not be used to estimate propagation delays pin no symbol name and function 6 clr asyncronous reset - direct input 2 d data input 1 ck clock input (low to high, edge triggered) 7 pr asyncronous set - direct input 5 q true flip-flop output 3 q complement flip-flop output 4 gnd ground (0v) 8v cc positive supply voltage inputs outputs function clr pr d ck q q l h x x l h clear h l x x h l preset l lxxhh hhl lh hhh hl hhx q n q n no change
74v2g74 3/13 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied recommended operating conditions 1) v in from 30% to 70% of v cc symbol parameter value unit v cc supply voltage -0.5 to +7.0 v v i dc input voltage -0.5 to +7.0 v v o dc output voltage -0.5 to v cc + 0.5 v i ik dc input diode current - 20 ma i ok dc output diode current - 20 ma i o dc output current 25 ma i cc or i gnd dc v cc or ground current 50 ma t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage 2 to 5.5 v v i input voltage 0 to 5.5 v v o output voltage 0 to v cc v t op operating temperature -55 to 125 c dt/dv input rise and fall time (note 1) (v cc = 3.3 0.3v) (v cc = 5.0 0.5v) 0 to 100 0to20 ns/v
74v2g74 4/13 dc specifications symbol parameter test condition value unit v cc (v) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. v ih high level input voltage 2.0 1.5 1.5 1.5 v 3.0 to 5.5 0.7v cc 0.7v cc 0.7v cc v il low level input voltage 2.0 0.5 0.5 0.5 v 3.0 to 5.5 0.3v cc 0.3v cc 0.3v cc v oh high level output voltage 2.0 i o =-50 m a 1.9 2.0 1.9 1.9 v 3.0 i o =-50 m a 2.9 3.0 2.9 2.9 4.5 i o =-50 m a 4.4 4.5 4.4 4.4 3.0 i o =-4 ma 2.58 2.48 2.4 4.5 i o =-8 ma 3.94 3.8 3.7 v ol low level output voltage 2.0 i o =50 m a 0.0 0.1 0.1 0.1 v 3.0 i o =50 m a 0.0 0.1 0.1 0.1 4.5 i o =50 m a 0.0 0.1 0.1 0.1 3.0 i o =4 ma 0.36 0.44 0.55 4.5 i o =8 ma 0.36 0.44 0.55 i i input leakage current 0to 5.5 v i = 5.5v or gnd 0.1 1 1 m a i cc quiescent supply current 5.5 v i =v cc or gnd 22020 m a
74v2g74 5/13 ac electrical characteristics (input t r =t f = 3ns) (*) voltage range is 3.3v 0.3v (**) voltage range is 5.0v 0.5v capacitive characteristics 1) c pd is defined as the value of the ic's internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) =c pd xv cc xf in +i cc symbol parameter test condition value unit v cc (v) c l (pf) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. t plh t phl propagation delay time ck to q or q 3.3 (*) 15 6.7 11.9 1.0 14.0 1.0 14.0 ns 3.3 (*) 50 9.2 15.4 1.0 17.5 1.0 17.5 5.0 (**) 15 4.6 7.3 1.0 8.5 1.0 8.5 5.0 (**) 50 6.1 9.3 1.0 10.5 1.0 10.5 t plh t phl propagation delay time pr or clr to qorq 3.3 (*) 15 7.6 12.3 1.0 14.5 1.0 14.5 ns 3.3 (*) 50 10.1 15.8 1.0 18.0 1.0 18.0 5.0 (**) 15 4.8 7.7 1.0 9.0 1.0 9.0 5.0 (**) 50 6.3 9.7 1.0 11.0 1.0 11.0 t w ck pulse width high or low 3.3 (*) 6.0 7.0 7.0 ns 5.0 (**) 5.0 5.0 5.0 t w pr or clr pulse width low 3.3 (*) 6.0 7.0 7.0 ns 5.0 (**) 5.0 5.0 5.0 t s setup time d to ck high or low 3.3 (*) 6.0 7.0 7.0 ns 5.0 (**) 5.0 5.0 5.0 t h hold time d to ck high or low 3.3 (*) 0.5 0.5 0.5 ns 5.0 (**) 0.5 0.5 0.5 t rem removal time pr or clr to ck 3.3 (*) 5.0 5.0 5.0 ns 5.0 (**) 3.0 3.0 3.0 f max maximum clock frequency 3.3 (*) 15 80 125 70 70 mhz 3.3 (*) 50 50 75 45 45 5.0 (**) 15 130 170 110 110 5.0 (**) 50 90 115 75 75 symbol parameter test condition value unit v cc (v) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. c in input capacitance 3.3 4101010pf c pd power dissipation capacitance (note 1) 3.3 f in = 10mhz 22 pf
74v2g74 6/13 test circuit c l =15/50pf or equivalent (includes jig and probe capacitance) r t =z out of pulse generator (typically 50 w ) waveform 1: propagation delays, setup and hold times (d to ck), ck maximum frequency , ck minimum pulse width (f=1mhz; 50% duty cycle)
74v2g74 7/13 waveform 2: propagation delays minimum pulse width (clr and pr) (f=1mhz; 50% duty cycle) waveform 3: recovery time (f=1mhz; 50% duty cycle)
74v2g74 8/13 waveform 4: pulse widths
74v2g74 9/13 dim. mm. mils min. typ max. min. typ. max. a 0.90 1.45 35.4 57.1 a1 0.00 0.15 0.0 5.9 a2 0.90 1.30 35.4 51.2 b 0.22 0.38 8.6 14.9 c 0.09 0.20 3.5 7.8 d 2.80 3.00 110.2 118.1 e 2.60 3.00 102.3 118.1 e1 1.50 1.75 59.0 68.8 e 0 .65 25.6 e1 1.95 76.7 l 0.35 0.55 13.7 21.6 sot23-8l mechanical data
74v2g74 10/13 dim. mm. mils min. typ max. min. typ. max. a 0.80 1.10 31.5 43.3 a1 0.00 0.10 0.0 3.9 a2 0.80 1.00 31.5 34.9 b 0.13 0.28 5.1 11.0 c 0.10 0.18 3.9 7.1 d 1.80 2.20 70.9 86.6 e 1.80 2.40 70.9 94.5 e1 1.15 1.35 45.3 53.1 e 0.5 19.7 e1 1.5 59.0 l 0.10 0.30 3.9 11.8 sot323-8l mechanical data
74v2g74 11/13 dim. mm. inch min. typ max. min. typ. max. a 180 7.086 c 12.8 13.0 13.2 0.504 0.512 0.519 d 20.2 0.795 n 60 2.362 t 14.4 0.567 ao 3.13 3.23 3.33 0.123 0.127 0.131 bo 3.07 3.17 3.27 0.120 0.124 0.128 ko 1.27 1.37 1.47 0.050 0.054 0.0.58 po 3.9 4.0 4.1 0.153 0.157 0.161 p 3.9 4.0 4.1 0.153 0.157 0.161 tape & reel sot23-xl mechanical data
74v2g74 12/13 dim. mm. inch min. typ max. min. typ. max. a 175 180 185 6.889 7.086 7.283 c 12.8 13 13.2 0.504 0.512 0.519 d 20.2 0.795 n 59.5 60 60.5 2.362 t 14.4 0.567 ao 2.25 0.088 bo 2.7 0.106 ko 1.2 0.047 po 3.98 4 4.2 0.156 0.157 0.165 p 3.98 4 4.2 0.156 0.157 0.165 tape & reel sot323-xl mechanical data
74v2g74 13/13 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco singapore - spain - sweden - switzerland - united kingdom - united states. ? http://www.st.com


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